1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
A known test apparatus for testing a device under test such as a semiconductor chip includes a plurality of test circuits, as shown in Patent Documents 1 and 2, for example. In this case, the test circuits preferably operate in synchronization.    Patent Document 1: International Publication WO 2003/062843    Patent Document 2: Japanese Patent Application Publication No. 2007-52028
Usually, each test circuit operates according to a program or sequence provided thereto in advance. In a conventional test apparatus, the test circuits are made to operate in synchronization by beginning the execution of the programs or the like in synchronization.
However, when a large number of tests are performed, causing the execution start timings of the programs to be synchronized in the test circuits may be insufficient to achieve synchronous operation. For example, during execution of a program, there may be cases where a subsequent step is preferably executed in synchronization on a condition that all of a set of predetermined test circuits are in a standby state.
In this case, if each program is designed such that the execution time of the program to be executed until the standby state is reached is the same in each test circuit, subsequent testing can be executed in synchronization by synchronizing the timing at which execution of the program begins. However, designing such programs requires significant effort.